Hardware & EDA Tooling .

Compiles SystemVerilog to a smaller gate netlist, cuts an 836K-gate benchmark by 80 percent, and proves it still computes the same thing.

A C++ compiler that turns SystemVerilog into a smaller gate netlist and proves it still computes the same thing. Six optimization passes cut an 836K-gate benchmark by 80 percent, and optimizing independent logic regions on a work-stealing pool runs 3.0 to 3.5 times faster on 16 threads, with identical output at any thread count.

Generates synthesizable Verilog from JSON; all 1,200 generated configurations synthesize in Yosys.

A C++ generator that turns JSON design descriptions into synthesizable Verilog: module hierarchy, ports, connectivity, inserted pipeline and adapter logic. Graph checks run before anything is written. 1,200 generated configurations all synthesize in Yosys, and on 1,000 deliberately broken descriptions invalid output drops from 766 files to none.

Clock, reset and CDC checks that found all 570 injected bugs with no false alarms, plus a targeted testbench for each.

A static checker for clock domains, reset trees, synchronizers, clock gating and cross-domain paths in Verilog, with 16 rules and a fix for each finding. For every violation it writes and runs a targeted testbench and draws the waveform at the first hazard. It found all 570 bugs injected into 870 generated designs with no false alarms, and the tests reproduced 89 percent of them.