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Systems & Performance .

C++ where every thread and every cache line counts, measured against the libraries people actually use.

7 projects

  • C++17
  • CMake
  • Python
  • Linux
  • Multithreading
  • PostgreSQL
  • Verilog
  • Yosys

Proxima

The index that beats the libraries

SIMD distance kernels in C++17: 1.8 times faster than hnswlib and 2.5 times faster than FAISS at 0.999 recall.

Everyone imports a vector search library. I wrote my own in C++ and made it win. It answers nearest neighbor queries 1.8 times faster than hnswlib and 2.5 times faster than FAISS, at 0.999 recall, on a single thread.

  • C++17
  • SIMD/AVX2
  • pybind11
  • CMake
  • Python
  • NumPy
also in Search

BlockStore

A storage engine that never loses an acknowledged write

A block cache, batched parallel reads and 64 lock partitions: 3.5 times the read throughput on 16-block batches under O_DIRECT.

A multithreaded block storage engine in C++17 for Linux: block reads and writes, atomic batches, snapshots and CRC-32C checksums, with crash recovery from a write-ahead log and double-buffered checkpoints. Validated by 35 fault-injection scenarios that crash it at every file-system call, flip every byte of its metadata, and kill it mid-write with SIGKILL.

  • C++17
  • Linux
  • POSIX I/O
  • Write-ahead logging
  • Multithreading
  • CMake
also in Data

LogicForge

A parallel compiler that shrinks circuits

A work-stealing pool runs 3.0 to 3.5 times faster on 16 threads, with identical output at any thread count.

A C++ compiler that turns SystemVerilog into a smaller gate netlist and proves it still computes the same thing. Six optimization passes cut an 836K-gate benchmark by 80 percent, and optimizing independent logic regions on a work-stealing pool runs 3.0 to 3.5 times faster on 16 threads, with identical output at any thread count.

  • C++17
  • CMake
  • SystemVerilog
  • Multithreading
  • Work stealing
  • ASan / TSan
also in Hardware

Fleet Guard

Catching driving regressions before a build ships

A deterministic C++17 driving simulator running about 4,000 drives a second on 22 threads.

A validation platform for autonomous-driving software builds. It replays the same seeded scenarios through a known-good build and a release candidate, compares what the two did, classifies every regression, and turns each cluster of failures into a report an engineer can reproduce with one command. One 100,000-drive campaign runs end to end in 52 seconds.

  • C++17
  • Python
  • PostgreSQL
  • FastAPI
  • Prometheus
  • Grafana

DistCompile

A build farm that never compiles the same thing twice

Content-hash caching ran the compiler 84 percent fewer times than make over a scripted 20-step edit workload.

A distributed build engine for C and C++. A gRPC coordinator schedules the build graph out of PostgreSQL, workers pull tasks and survive crashes, and every result is cached by content hash. Over a scripted 20-step edit workload it ran the compiler 84 percent fewer times than make, and never recompiled code it had already built.

  • C++17
  • gRPC
  • Protocol Buffers
  • PostgreSQL
  • Docker
  • CMake
also in Backend

rtlgen

Synthesizable Verilog from a structured description

C++17 with graph checks before a single file is written, built and tested under ASan and UBSan.

A C++ generator that turns JSON design descriptions into synthesizable Verilog: module hierarchy, ports, connectivity, inserted pipeline and adapter logic. Graph checks run before anything is written. 1,200 generated configurations all synthesize in Yosys, and on 1,000 deliberately broken descriptions invalid output drops from 766 files to none.

  • C++17
  • CMake
  • Verilog
  • Yosys
  • Icarus Verilog
  • Python
also in Hardware

clockguard

Clock, reset and CDC checks with targeted testbenches

A C++17 static checker with 16 rules, built on Yosys and kept clean under ASan and UBSan.

A static checker for clock domains, reset trees, synchronizers, clock gating and cross-domain paths in Verilog, with 16 rules and a fix for each finding. For every violation it writes and runs a targeted testbench and draws the waveform at the first hazard. It found all 570 bugs injected into 870 generated designs with no false alarms, and the tests reproduced 89 percent of them.

  • C++17
  • Yosys
  • Verilog
  • Icarus Verilog
  • Python
  • Clock-domain crossing
also in Hardware

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